diff options
| author | henryk <henryk@6dc7ffe9-61d6-0310-9af1-9938baff3ed1> | 2007-11-23 10:30:50 +0000 |
|---|---|---|
| committer | henryk <henryk@6dc7ffe9-61d6-0310-9af1-9938baff3ed1> | 2007-11-23 10:30:50 +0000 |
| commit | 062f55ca3ea77ebcace83aab4772c9cd3f28ec34 (patch) | |
| tree | 22581f5054c35007e1a34113dd77f4818a3a67e3 /openpicc/os/core | |
| parent | ae5309d51c484ddf052ee19fd2a76c058e927bcb (diff) | |
Commit status quo (pending cleanup of the debug and experimental code that I added during the last week)
Change freertos code to not mask FIQ, this finally makes the FIQ working (with approx 700ns +/- 100ns latency; yeah!) and therefore reception starts working
Change to two times oversampling (keep four times oversampling code ifdef'd, extract all the magical values to a header file) because at four times oversampling every other sample is very close to
a possible data edge and therefore not reliable
git-svn-id: https://svn.openpcd.org:2342/trunk@347 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
Diffstat (limited to 'openpicc/os/core')
| -rw-r--r-- | openpicc/os/core/ARM7_AT91SAM7S/portISR.c | 4 | ||||
| -rw-r--r-- | openpicc/os/core/ARM7_AT91SAM7S/portmacro.h | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/openpicc/os/core/ARM7_AT91SAM7S/portISR.c b/openpicc/os/core/ARM7_AT91SAM7S/portISR.c index 507712e..6f92c24 100644 --- a/openpicc/os/core/ARM7_AT91SAM7S/portISR.c +++ b/openpicc/os/core/ARM7_AT91SAM7S/portISR.c @@ -178,7 +178,7 @@ vPortDisableInterruptsFromThumb (void) { asm volatile ("STMDB SP!, {R0} \n\t" /* Push R0. */ "MRS R0, CPSR \n\t" /* Get CPSR. */ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "ORR R0, R0, #0x80 \n\t" /* Disable IRQ, don't disable FIQ. */ "MSR CPSR, R0 \n\t" /* Write back modified value. */ "LDMIA SP!, {R0} \n\t" /* Pop R0. */ "BX R14"); /* Return back to thumb. */ @@ -206,7 +206,7 @@ vPortEnterCritical (void) /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ asm volatile ("STMDB SP!, {R0} \n\t" /* Push R0. */ "MRS R0, CPSR \n\t" /* Get CPSR. */ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ + "ORR R0, R0, #0x80 \n\t" /* Disable IRQ, don't disable FIQ. */ "MSR CPSR, R0 \n\t" /* Write back modified value. */ "LDMIA SP!, {R0}"); /* Pop R0. */ diff --git a/openpicc/os/core/ARM7_AT91SAM7S/portmacro.h b/openpicc/os/core/ARM7_AT91SAM7S/portmacro.h index 6b25ec5..da980a7 100644 --- a/openpicc/os/core/ARM7_AT91SAM7S/portmacro.h +++ b/openpicc/os/core/ARM7_AT91SAM7S/portmacro.h @@ -238,7 +238,7 @@ extern void vPortEnableInterruptsFromThumb (void) __attribute__ ((naked)); asm volatile ( \ "STMDB SP!, {R0} \n\t" /* Push R0. */ \ "MRS R0, CPSR \n\t" /* Get CPSR. */ \ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \ + "ORR R0, R0, #0x80 \n\t" /* Disable IRQ, don't diable FIQ. */ \ "MSR CPSR, R0 \n\t" /* Write back modified value. */ \ "LDMIA SP!, {R0} " ) /* Pop R0. */ |